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integrated silicon solution, inc. www.issi.com 1 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a is24c02a/04a/08a/16a 2-wire (i 2 c) 2k/4k/8k/16k-bit serial eeprom
2 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a t able of contents features ............3 description ..............3 functional b lock diagram ...........4 pin confguration & description ............5 device operations .............6 absolute maximum ratings ............14 dc characteristics ............14 ac characteristics ............15 ordering information ............17 packaging information .............18
integrated silicon solution, inc. www.issi.com 3 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a 2k-bit/4k-bit/8k-bit/16k-bit 2-wire serial cmos eeprom description the is24c02a, is24c04a, is24c08a, and is24c16a are eeprom devices that use the industrial standard 2-wire interface for communica - tions. the is24c02a, is24c04a, is24c08a, and is24c16a contain a memory array of 2k-bits (256 x 8), 4k-bits (512 x 8), 8k-bits (1,024 x 8), and 16k-bits (2,048 x 8), respectively. each device is organized into 16 byte pages for page write mode. this eeprom operates in a wide voltage range of 1.8v to 5.5v to be compatible with most application voltages. issi designed this device family to be a practical, low-power 2-wire eeprom solution. the devices are offered in lead-free, rohs, halogen free or green. the available package types are 8-pin soic/sop, tssop, pdip, msop, dfn and csp. the is24c02a/04a/08a/16a maintains compat- ibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. the simple bus consists of the serial clock wire (scl) and the serial data wire (sda). using the bus, a master device such as a microcontroller is usually connected to one or more slave devices such as this device. the bit stream over the sda line includes a series of bytes, which identifes a particular slave device, an instruction, an address within that slave device, and a series of data, if ap - propriate. the is24c02a/04a/08a/16a has a write protect pin (wp) to allow blocking of any write instruction transmitted over the bus. f eatures ? two-wire serial interface, i 2 c tm compatible C bi-directional data transfer protocol ? wide voltage operation C vcc = 1.8v to 5.5v ? 400 khz (2.5v) and 1 mhz (5.0v) compatible ? low power C standby current less than 1 a (1.8v) C read current less than 2 ma (5.0v) C write current less than 3 ma (5.0v) ? hardware data protection C write protect pin ? sequential read feature ? filtered inputs for noise suppression ? self time write cycle with auto clear 5 ms max @ 2.5v ? memory organization C is24c02a: 256x8 (one block of 256 bytes) C is24c04a: 512x8 (two blocks of 256 bytes) C is24c08a: 1024x8 (four blocks of 256 bytes) C is24c16a: 2048x8 (eight blocks of 256 bytes) ? 16 byte page write buffer ? high reliability C endurance: 1,000,000 cycles C data retention: 100 years ? industrial temperature grade ? packages: soic/sop, tssop, pdip, msop, dfn, csp copyright ? 2008 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip - ment, aerospace systems, or for other applications planned to support or sustain life. it is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and prior placing orders for products.
4 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control eeprom array y decoder data register clock di/o ack 8 5 6 7 4 gnd wp scl sda vcc nmos 1 2 3 a2 a1 a0 functional block diagram
integrated silicon solution, inc. www.issi.com 5 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wire-or'ed with other open drain or open collector outputs. the sda bus requires a pullup resistor to vcc. a0, a1, a2 the a0, a1 and a2 are the device address inputs. the is24c02a uses the a0, a1, and a2 for hardware addressing and a total of 8 devices may be used on a single bus system. when the a0, a1, or a2 inputs are left foating, the input internally defaults to zero. pin configuration 8-pin soic, tssop, msop, pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda the is24c04a uses a1 and a2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system. the a0 pin is a no connect in the is24c04a. when the a1 or a2 input is left foating, the input internally defaults to zero. the is24c08a only uses the a2 input for hardwire addressing and a total of two devices may be addressed on a single bus system. the a0 and a1 pins are no connects in the is24c08a. when the a2 input is left foating, the input internally defaults to zero. these pins are not used by is24c16a . the a0, a1, and a2 pins are no connects in the is24c16a. wp wp is the write protect pin. if the wp pin is tied to v c c on the is24c02a, is24c04a, is24c08a and is24c016a, the entire array becomes write protected (read only). when wp is tied to gnd or left foating normal read/write operations are allowed to the device. pin configuration 8-pad dfn 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda (top view)
6 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a device operatio n is24c02a/04a/08a/16a features serial communication and supports a bi-directional 2-wire bus transmission protocol called i 2 c tm . 2-wire b us the two-wire bus is defned as a serial data line (sda), and a serial clock line (scl). the protocol defnes any device that sends data onto the sda bus as a transmitter, and the receiving devices as receivers. the bus is controlled by master device that generates the scl, controls the bus access, and generates the stop and start conditions. the is24c02a/04a/08a/16a is the slave device on the bus. the b us protocol: C data transfer may be initiated only when the bus is not busy C during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. start condition the start condition precedes all commands to the device and is defned as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defned as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the is24c02a/04a/08a/16a contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. the reset is caused when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode power consumption is reduced in standby mode. the is24c02a/04a/08a/16a will enter standby mode: a) at power-up, and remain in it until scl or sda toggles; b) following the stop signal if a no write operation is initiated; or c) following any internal write operation.
integrated silicon solution, inc. www.issi.com 7 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a page write the is24c02a/04a/08a/16a is capable of 16-byte page- write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the frst data word is transferred, the master device can transmit up to 15 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the four lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is incremented from the last byte of a page, it returns to the frst byte of that page. if the master device should transmit more than 16 bytes prior to issuing the stop condition, the address counter will roll over, and the previously written data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the is24c02a/04a/08a/16a in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the is24c02a/04a/08a/16a initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the is24c02a/04a/08a/16a has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write operatio n b yte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w set to zero) to the slave device. after the slave generates an ack, the master sends the byte address that is to be written into the address pointer of the is24c02a/04a/08a/16a. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the is24c02a/04a/08a/16a acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave devices it is requesting. the slave device (fig. 5) address is 8 bits. the four most signifcant bits of the slave address are fxed as 1010 for the is2402a/04a/08a/16a. the next three bits of the slave address are specifc for each of the eeprom. the bit values enable access to multiple memory blocks or multiple devices. the is24c02a uses the three bits a0, a1, and a2 in a comparison with the hard-wired input values on the a0, a1, and a2 pins. up to eight is24c02a units may share the 2-wire bus. the is24c04a uses the bit b0 to address either the upper or the lower 256 byte block in the device. also, the bits a1 and a2 are used in a comparison with the hard-wired input values on the a1 and a2 pins. up to four is24c04a units may share the 2-wire bus. the is24c08a uses the bits b0 and b1 to address one of the four 256 byte blocks in the device. also, the bit a2 is used in a comparison with the hard-wired input value on the a2 pin. up to two is24c08a units may share the 2-wire bus. the is24c16a uses the bits b0, b1, and b2 to address one of the eight 256 byte blocks in the device. the last bit of the slave address specifes whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master transmits the start condition and slave address byte (fig. 5), the appropriate 2-wire slave (eg. is24c02a/04a/08a/16a) will respond with ack on the sda line. the slave will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the selected eeprom then prepares for a read or write operation by monitoring the bus.
8 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a read operation read operations are initiated in the same manner as write operations, except that the (r/ w ) bit of the slave address is set to 1. there are three read operation options: current address read, random address read and sequential read. current address read the is24c02a/04a/08a/16a contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/w bit set to 1), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the is24c02a/04a/08a/16a discontinues transmission. if 'n' is the last byte of the memory, the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device frst performs a 'dummy' write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the is24c02a/04a/08a/16a acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the eeprom then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the is24c02a/04a/08a/16a sends the initial byte sequence, the master device now responds with an ack indicating it requires additional data from the is24c02a/04a/08a/16a. the eeprom continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of 255, 511, 1023, or 2047 (depending on the device) is reached, the address counter rolls over to address 0, and the device continues to output data. (refer to figure 10. sequential read diagram).
integrated silicon solution, inc. www.issi.com 9 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a stop condition scl sda start condition figure 3. start and stop conditions scl sda master transmitter/ receiver is24cxx vcc figure 1. typical system bus conf iguration t aa data output from transmitter scl from master data output from receiver 18 9 ack t aa figure 2. output a ckn owledge
10 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a figure 5. s lave address figure 4. d ata v alidity p rotocol scl sda data stable data stable data change 7 bit 43 1 2 5 6 0 r/w b0 b1 b2 0 1 0 1 lsb is24c16a is24c08a msb 7 bit 43 1 2 5 6 0 r/w a0 a1 a2 0 1 0 1 is24c02a 7 bit 43 1 2 5 6 0 r/w b0 b1 a2 0 1 0 1 7 bit 43 1 2 5 6 0 r/w b0 a1 a2 0 1 0 1 is24c04a figure 6. byte write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/w a c k a c k a c k data device address byte address
integrated silicon solution, inc. www.issi.com 11 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a figure 9. random address read sda bus activity a c k a c k a c k data n byte address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/w figure 7. p age w rite sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) byte address (n) device address s t o p a c k data (n+15) r/w figure 8. current address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w
12 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a figure 10. seq uential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
integrated silicon solution, inc. www.issi.com 13 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a ac wave forms f igure 11. b us timing t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp 8th bit ack word n stop condition start condition t wr scl sda f igure 12. write cycle timing
14 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a dc electrical characteristics industrial (t a = -40 o c to +85 o c) symbol parameter test conditions min. max. unit i c c 1 operating current read at 400 khz (vcc = 5v) 2.0 ma i c c 2 operating current write at 400 khz (vcc = 5v) 3.0 ma i s b 1 standby current vcc = 1.8v 1 a i s b 2 standby current vcc = 2.5v 2 a i s b 3 standby current vcc = 5.0v 6 a v o l 1 output low voltage v c c = 1.8v, i o l = 0.15 ma 0.2 v v o l 2 output low voltage v c c = 2.5v, i o l = 3 ma 0.4 v v i h input high voltage v c c x 0.7 v c c + 0.5 v v i l input low voltage C1.0 v c c x 0.3 v i l i input leakage current v i n = v c c max. 3 a i l o output leakage current 3 a notes: v i l min and v i h max are reference only and are not tested. ab solute maximum ratings (1) symbol parameter value unit v s supply voltage C0.5 to +6.5 v v p voltage on any pin C0.5 to vcc + 0.5 v t b i a s temperature under bias C55 to +125 c t s t g storage temperature C65 to +150 c i o u t output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause per - manent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacita nce (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c o u t output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, vcc = 5.0v.
integrated silicon solution, inc. www.issi.com 15 rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a ac electrical characteristics industrial (t a = -40 o c to +85 o c) 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v (1) symbol parameter (2) min. max. min. max. min. max. unit f s c l scl clock frequency 0 100 0 400 0 1000 khz t noise suppression time (1) 100 50 50 ns t l o w clock low period 4.7 1.2 0.6 s t h i g h clock high period 4 0.6 0.4 s t b u f bus free time before new transmission (1) 4.7 1.2 0.5 s t s u : s t a start condition setup time 4 0.6 0.25 s t s u : s t o stop condition setup time 4 0.6 0.25 s t h d : s t a start condition hold time 4 0.6 0.25 s t s u : d a t data in setup time 100 100 100 ns t h d : d a t data in hold time 0 0 0 ns t s u : w p wp pin setup time 4 0.6 0.6 s t h d : w p wp pin hold time 4.7 1.2 1.2 s t d h data out hold time (scl low to sda data out change) 100 50 50 ns t a a clock to output (scl low to sda data out valid) 100 3500 50 900 50 400 ns t r scl and sda rise time (1) 1000 300 300 ns t f scl and sda fall time (1) 300 300 100 ns t w r write cycle time 5 5 5 ms note: 1. this parameter is characterized but not 100% tested. 2. the timing is referenced to half vcc level.
16 integrated silicon solution, inc. www.issi.com rev. l 08/06/09 is24c02a is24c04a is24c08a is24c16a ordering inf ormation industrial range*: -40c to +85c, lead-free voltage range part number* package type* (8-pin) 1.8v to 5.5v is24c02a-2gli-tr 150-mil soic (jedec) is24c02a-2zli-tr 3 x 4.4 mm tssop is24c02a-2sli-tr 120-mil msop 1.8v to 5.5v is24c04a-2gli-tr 150-mil soic (jedec) is24c04a-2zli-tr 3 x 4.4 mm tssop is24c04a-2pli-tr 300-mil pdip is24c04a-2dli-tr 2 x 3 mm dfn 1.8v to 5.5v is24c08a-2gli-tr 150-mil soic (jedec) is24c08a-2zli-tr 3 x 4.4 mm tssop is24c08a-2sli-tr 120-mil msop is24c08a-2pli-tr 300-mil pdip is24c08a-2dli-tr 2 x 3 mm dfn is24c08a-2cli-tr csp 1.8v to 5.5v is24c16a-2gli-tr 150-mil soic (jedec) is24c16a-2zli-tr 3 x 4.4 mm tssop is24c16a-2sli-tr 120-mil msop is24c16a-2pli-tr 300-mil pdip is24c16a-2dli-tr 2 x 3 mm dfn is24c16a-2cli-tr csp * 1. contact issi sales representatives for availability and other package information. 2. the listed part numbers are packed in tape and reel -tr (4k per reel). udfn/dfn is 5k per reel. 3. for tube/bulk packaging, remove -tr at the end of the p/n. 4. refer to issi website for related declaration document on lead free, rohs, halogen free, or green, whichever is applicable. 5. issi offers industrial grade for commercial applications (0 o c to +70 o c).
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